Memory test algorithms are written to uncover faults with storage cells and the access to these storage cells arising from improper design, lack of design margins or processing deficiencies. Generally, these algorithms are written to be extensive and exhaustive to ensure that no bit defects, either hard defects or intermittent failures find their way into the field. As such, in addition to straight forward writing and reading from storage cells, various methods of disturbing the bits have been devised and employed. Some algorithms write and read at one voltage and read and write at another voltage to check for slew margins.
Data retention tests are also being performed with more frequency lately as memory cells are required to retain data in a sleep mode or what is commonly referred to as “data retention” mode. In this mode, storage cells have reduced voltages applied across them to minimize leakage currents during the standby condition. As more and more tests are applied and as memory sizes grow in embedded memory applications, memory test times have been a substantial part of the overall test time on products despite the use of design for test (DFT) and built-in self test (BIST). Accordingly, there is a growing need for the reduction of the overall testing time in the manufacturing and testing of semiconductor memory devices.
Several other trends presently exist in the semiconductor and electronics industry. Devices are continually being made smaller, faster and requiring less power. Accordingly, in the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. To achieve high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers, that are generally produced from bulk silicon. In order to accomplish such high densities, smaller feature sizes, smaller separations between features, and more precise feature shapes are required in integrated circuits fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges).
It can be appreciated that the effects of scaling may be even more noticeable in certain types of semiconductor devices, such as static random access memory (SRAM), for example, which incorporate multiple densely packed transistors that require matched electrical properties. As semiconductor features are aggressively reduced, for example, local mismatches between SRAM transistors have increased; presenting greater problems that may limit the usable feature size. Additionally, small misalignments between any two layers (e.g., moat and gate) have resulted in larger mismatches for more advanced technology nodes. For example, in situations where there is misalignment, a right transistor Vt may be altered more or less than a left transistor Vt, thereby disadvantageously creating transistor mismatch.
Semiconductor memories can, for example, be characterized as volatile memories (e.g., RAMs) or nonvolatile memories, where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. In SRAM, for example, each memory cell includes transistor-based circuitry that implements a bistable latch, which relies on transistor gain and positive (e.g., reinforcing) feedback so that it can only assume one of two possible states, namely on (state 1) or off (state 2). The latch can be programmed or induced to change from one state to the other through the application of a voltage or other external stimuli. This arrangement is desirable for a memory cell since a state written to the cell will be retained until the cell is reprogrammed.
DRAMs on the other hand implement a capacitor that is either charged or discharged to store the on (state 1) or off (state 2) state of a cell. Capacitors discharge over time, however, and DRAMs must therefore be periodically ‘refreshed’. Also, a bistable latch can generally be switched between states much faster than the amount of time it takes to charge or discharge a capacitor. Accordingly, SRAMs are a desirable type of memory for certain types of applications.
SRAM is typically arranged as a matrix of memory cells fabricated in an integrated circuit chip, and address decoding in the chip allows access to each cell for read/write functions. SRAM memory cells use active feedback from cross-coupled inverters in the form of a latch to store or “latch” a bit of information. These SRAM memory cells are often arranged in rows so that blocks of data such as words or bytes can be written or read simultaneously. Standard SRAM memory cells have many variations. The basic CMOS SRAM cell generally includes two n-type (nMOS) pull-down or drive transistors and two p-type (pMOS) load transistors in a cross-coupled inverter configuration, with two additional nMOS select transistors added to make up a six-transistor cell (a 6T cell). Additionally, application specific SRAM cells can include an even greater number of transistors. Since a plurality of transistors are utilized in SRAM requiring matched electrical characteristics, and since the negative effects of matching may become more prevalent as transistor widths are reduced, transistor mismatching issues may present themselves to a great degree in SRAM, particularly as that type of memory is continually scaled down.
Accordingly, it would be desirable to obtain a testing technique that reduces memory testing time while allowing transistors to be scaled down, particularly in SRAM devices.